Job Profile | Job Location | Description | Date of Opening |
---|---|---|---|
Job Profile |
Job Location San Jose, CA |
Description * Perform physical verification (DRC, LVS) using Calibre at full-chip level.
* Collaborate with design teams to resolve verification and layout... |
Date of Opening 2/15/2025 |
Job Profile |
Job Location San Jose, CA |
Description Experience with PCIe, Ethernet, slow speed interfaces like I2C, SPI, MDIO etc.
* Ability to independently develop test plans, test sequences... |
Date of Opening 3/8/2025 |
Job Profile |
Job Location San Jose, CA |
Description Experience with PCIe, Ethernet, slow speed interfaces like I2C, SPI, MDIO etc.
* Ability to independently develop test plans, test sequences... |
Date of Opening 3/7/2025 |
Job Profile |
Job Location San Jose, CA |
Description * Perform physical verification (DRC, LVS) using Calibre at full-chip level.
* Collaborate with design teams to resolve verification and layout... |
Date of Opening 2/26/2025 |
1 Senior Electrical Engineers from ASICSoft submitted salaries.
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